Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10921
-gerrit
commit 75f6aaf519d4a866c914230d8507e8da4e33371f Author: Lee Leahy leroy.p.leahy@intel.com Date: Tue Jul 14 17:36:01 2015 -0700
Braswell: Add memory type and PMIC definitions
Add new definitions for memory type and PMIC configuration. Matches chromium tree at 927026db.
BRANCH=none BUG=None TEST=Build and run on strago
Change-Id: I0b3e895a95bda18de19e433477fab11f3adc270b Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/braswell/chip.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index d70aa9b..191fc01 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -30,8 +30,12 @@ #include <fsp_util.h> #include <soc/pci_devs.h>
-#define SVID_CONFIG1 1 -#define SVID_CONFIG3 3 +#define SVID_CONFIG1 1 +#define SVID_CONFIG3 3 +#define SVID_PMIC_CONFIG 8 + +#define MEM_DDR3 0 +#define MEM_LPDDR3 1
struct soc_intel_braswell_config { uint8_t enable_xdp_tap;