Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38606 )
Change subject: soc/intel/tigerlake: add memory configuration support ......................................................................
soc/intel/tigerlake: add memory configuration support
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/meminit.h A src/soc/intel/tigerlake/meminit.c 3 files changed, 205 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38606/1
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 532861d..c1bac36 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -25,6 +25,7 @@
romstage-y += espi.c romstage-y += gpio.c +romstage-y += meminit.c romstage-y += reset.c
ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h new file mode 100644 index 0000000..a99b033 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_TIGERLAKE_MEMINIT_H_ +#define _SOC_TIGERLAKE_MEMINIT_H_ + +#include <stddef.h> +#include <stdint.h> +#include <fsp/soc_binding.h> + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 +#define NUM_CHANNELS 8 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum lpddr4x_mem_info_read_type { + NOT_EXISTING, /* No memory in this channel */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct lpddr4x_spd_info { + enum lpddr4x_mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_lpddr4x_cfg { + /* SPD info */ + struct lpddr4x_spd_info spd; + + /* DQ mapping */ + uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map MC0 and MC1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; + + /* Set to true if only populating half the DRAM */ + bool half_populated; +}; + +/* Initialize default memory configurations for lpddr4x */ +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, struct mb_lpddr4x_cfg *board_cfg); + +#endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c new file mode 100644 index 0000000..4c2199b --- /dev/null +++ b/src/soc/intel/tigerlake/meminit.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <assert.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/meminit.h> +#include <spd_bin.h> +#include <string.h> + +/* If half populating DRAM, those channels would be 0 thru 3 */ +#define HALF_POPULATED_COUNT 4 + +enum dimm_enable_options { + ENABLE_BOTH_DIMMS = 0, + DISABLE_DIMM0 = 1, + DISABLE_DIMM1 = 2, + DISABLE_BOTH_DIMMS = 3 +}; + +/* Configure memory channel as unpopulated */ +#define MEM_CFG_EMPTY(_mem_cfg, _mc, _ch) \ + do { \ + _mem_cfg->DisableDimmMc ## _mc ## Ch ## _ch = DISABLE_BOTH_DIMMS; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 0 = 0; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 1 = 0; \ + } while (0) + +/* Configure memory channel with only dimm0 used */ +#define MEM_CFG_DIMM0(_mem_cfg, _mc, _ch, _data, _b_cfg) \ + do { \ + _mem_cfg->DisableDimmMc ## _mc ## Ch ## _ch = DISABLE_DIMM1; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 0 = _data; \ + _mem_cfg->MemorySpdPtr ## _mc ## _ch ## 1 = 0; \ + memcpy(&_mem_cfg->DqMapCpu2DramMc ## _mc ## Ch ## _ch, \ + &_b_cfg->dq_map[_mc * NUM_CHANNELS / 2 + _ch], \ + sizeof(_b_cfg->dq_map[_mc * NUM_CHANNELS / 2 + _ch])); \ + memcpy(&_mem_cfg->DqsMapCpu2DramMc ## _mc ## Ch ## _ch, \ + &_b_cfg->dqs_map[_mc * NUM_CHANNELS / 2 + _ch], \ + sizeof(_b_cfg->dqs_map[_mc * NUM_CHANNELS / 2 + _ch])); \ + } while (0) + + +static void spd_read_from_cbfs(const struct lpddr4x_spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct lpddr4x_spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + if (spd->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, struct mb_lpddr4x_cfg *board_cfg) +{ + const struct lpddr4x_spd_info *spd = &board_cfg->spd; + size_t spd_data_len; + uintptr_t spd_data_ptr; + + get_spd_data(spd, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + + MEM_CFG_DIMM0(mem_cfg, 0, 0, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 1, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 2, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 0, 3, spd_data_ptr, board_cfg); + + if (board_cfg->half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + MEM_CFG_EMPTY(mem_cfg, 1, 0); + MEM_CFG_EMPTY(mem_cfg, 1, 1); + MEM_CFG_EMPTY(mem_cfg, 1, 2); + MEM_CFG_EMPTY(mem_cfg, 1, 3); + } else { + MEM_CFG_DIMM0(mem_cfg, 1, 0, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 1, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 2, spd_data_ptr, board_cfg); + MEM_CFG_DIMM0(mem_cfg, 1, 3, spd_data_ptr, board_cfg); + } + + /* LPDDR4 does not allow interleaved memory */ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->ECT = board_cfg->ect; + mem_cfg->MrcSafeConfig = 0x1; +}