Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5613
-gerrit
commit f8340e91dc906fa85be3fa8a8a31e140c339aff6 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Tue Apr 29 20:13:22 2014 +1000
mainboard/asrock/e350m1: Use std memset/memcpy func over AGESA
Following the combined reasoning in: e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA feebd86 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
Change-Id: I801053e7ff5da2885aa282f84143c0399d766e26 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 249 ++++++++++++--------- .../asrock/e350m1/PlatformGnbPcieComplex.h | 98 ++++---- 2 files changed, 200 insertions(+), 147 deletions(-)
diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index ed20b59..3d28e8e 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,137 +18,177 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" +#include "BiosCallOuts.h" + +#include <string.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <string.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
-/*---------------------------------------------------------------------------------------*/ /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly * **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + void *BrazosPcieComplexListPtr; + void *BrazosPciePortPtr; + void *BrazosPcieDdiPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams;
+/** + * @brief Initialize Port descriptors + */ PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) - }, - #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) - }, - #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) + }, + /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ + { + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) + } };
+/** + * @brief Initialize Ddi descriptors + */ PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} - } + /* (DDI interface Lanes 8:11, DdA, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ + {ConnectorTypeLvds, Aux1, Hdp1} + }, + /* (DDI interface Lanes 12:15, DdB, ...) */ + { + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ + {ConnectorTypeDP, Aux2, Hdp2} + } };
PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
- // GNB PCIe topology Porting - - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); - - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); - if ( Status!= AGESA_SUCCESS) { - // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); - return; - } - - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + /** + * @brief GNB PCIe topology Porting + * + * Allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + AllocHeapParams.RequestedBufferSize = + sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + + /** + * Could not allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + if (Status!= AGESA_SUCCESS) { + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
+ ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr;
- ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 5efcd7d..dd6f7d7 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,53 +21,64 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> +#include <vendorcode/amd/agesa/f14/Lib/amdlib.h>
-//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/** + * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) + * + * GNB_GPP_PORT?_PORT_PRESENT + * 0:Disable 1:Enable + * + * GNB_GPP_PORT?_SPEED_MODE + * 0:Auto 1:GEN1 2:GEN2 + * + * GNB_GPP_PORT?_LINK_ASPM + * 0:Disable 1:L0s 2:L1 3:L0s+L1 + * + * GNB_GPP_PORT?_CHANNEL_TYPE - + * 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + * 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) + * + * GNB_GPP_PORT?_HOTPLUG_SUPPORT + * 0:Disable 1:Basic 3:Enhanced + */ + +/* GNB GPP 4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0
-//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0
-//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0
-//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0
-//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
-VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly);
-#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */