[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS setting

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting
......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board
design.
- Enable/Disable Xhci/Xdci
- Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none
BRANCH=none
TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim 
Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
3 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 3f980d1..a4542fb 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -218,6 +218,34 @@
    	FORCE_ENABLE,
    } CnviBtAudioOffload;

+	/* Tcss */
+        uint8_t TcssXhciEn;
+        uint8_t TcssXdciEn;
+
+	/*
+	 * Tcss Aux Orienation override
+	 * bits 0, 2, ... 10 control override for port
+	 * 	value: 1 - controlled by iom, 0 - controled by retimer
+	 * bits 1, 3, ... 11 orientation override for port
+	 * 	value: 0 - not swapped , 1 - swapped
+	 * Reference: IOM_TYPEC_SW_CONFIGURATION_3 in TGL EDS#575681
+	 */
+	uint8_t TcssAuxOri;
+
+	/* 
+	 * Tcss HSL Orientation override
+	 * bits 0, 2, ... 10 control override for port
+	 * bits 1, 3, ... 11 orientation override for port
+	 * Reference: IOM_TYPEC_SW_CONFIGURATION_4 in TGL EDS#575681
+	 */
+	uint8_t TcssHslOri;
+
+	/*
+	 * TypeC port GPIO setting
+	 * GPIO pin number for Type C Aux orienation setting when it's controlled by iom
+	 */
+	uint32_t IomTypeCPortPadCfg[8];
+
    /*
     * Override GPIO PM configuration:
     * 0: Use FSP default GPIO PM program,
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e..085689c 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,12 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* Tcss */
+	params->TcssHslOri = config->TcssHslOri;
+	params->TcssAuxOri = config->TcssAuxOri;
+	memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg,
+		sizeof(config->IomTypeCPortPadCfg));
+
    mainboard_silicon_init_params(params);
 }

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 6ed3dcd..88c790b 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -102,6 +102,10 @@
    m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
    m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;

+	/* Tcss */
+	m_cfg->TcssXhciEn = config->TcssXhciEn;
+	m_cfg->TcssXdciEn = config->TcssXdciEn;
+
    /* Enable Hyper Threading */
    m_cfg->HyperThreading = 1;
    /* Disable Lock PCU Thermal Management registers */