[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure THC

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41571 )

Change subject: soc/intel/tigerlake: Configure THC
......................................................................

soc/intel/tigerlake: Configure THC

Enable/Disable THCx though devicetree

BUG=None
BRANCH=None
TEST=Boot and check FSP log for THC setting

Signed-off-by: Wonkyu Kim 
Change-Id: If7683969161be67f68f441c28c80503de39079b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 18 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Wonkyu Kim: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 611a610..bdcd357 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -17,6 +17,11 @@
 #include <soc/soc_chip.h>
 #include <string.h>

+/* THC assignment definition */
+#define THC_NONE	0
+#define THC_0		1
+#define THC_1		2
+
 /*
  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
  * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
@@ -221,6 +226,19 @@
    else
    	params->VmdEnable = 0;

+	/* THC */
+	dev = pcidev_path_on_root(PCH_DEVFN_THC0);
+	if (!dev)
+		params->ThcPort0Assignment = 0;
+	else
+		params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE;
+
+	dev =  pcidev_path_on_root(PCH_DEVFN_THC1);
+	if (!dev)
+		params->ThcPort1Assignment = 0;
+	else
+		params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE;
+
    /* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;