Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 36: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
D'oh
D'oh-ne
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 38: REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */
BIOS spec places this before 0x6800.
This is the memory controller lock register. It should have been written by MRC already, and does not depend on the other lock bits. I'll keep the registers sorted in increasing offset values.