[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39110 )

Change subject: soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume
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soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume

This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and
Enable8254ClockGatingOnS3) depends on CONFIG_USE_LEGACY_8254_TIMER to
avoid discrepancy between S0 and S3 resume flow.

TEST=Able to boot to TianoCore in both S0 and S3 resume without
any hangs and errors.

Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/icelake/fsp_params.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39110/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index dc4a2a8..f1b8446 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -261,7 +261,7 @@

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
-	params->Enable8254ClockGatingOnS3 = 1;
+	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

/* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index 7514be1..334fac8 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -140,7 +140,7 @@

/* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
-	params->Enable8254ClockGatingOnS3 = 1;
+	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

/* S0ix */
    params->PchPmSlpS0Enable = config->s0ix_enable;