Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41867 )
Change subject: mb/gigabyte/ga-g41m-es2l: Prepare for a variant ......................................................................
mb/gigabyte/ga-g41m-es2l: Prepare for a variant
To ease the review of adding a variant (ga-g41m-combo) move a few things around without yet adding the variant.
Change-Id: I0b22731849e157b76be97dbe02a7538f1cea472d Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig M src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/early_init.c A src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h A src/mainboard/gigabyte/ga-g41m-es2l/superio.h R src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/gpio.c R src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/hda_verb.c A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb A src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c 10 files changed, 166 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/41867/1
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index fa6783d1..97f155a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -7,7 +7,7 @@ select CPU_INTEL_SOCKET_LGA775 select NORTHBRIDGE_INTEL_X4X select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_ITE_IT8718F + select SUPERIO_ITE_IT8718F if BOARD_GIGABYTE_GA_G41M_ES2L select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select PCIEXP_ASPM @@ -24,9 +24,17 @@ string default "gigabyte/ga-g41m-es2l"
+config VARIANT_DIR + string + default "ga-g41m-es2l" if BOARD_GIGABYTE_GA_G41M_ES2L + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER string - default "GA-G41M-ES2L" + default "GA-G41M-ES2L" if BOARD_GIGABYTE_GA_G41M_ES2L
config MAX_CPUS int diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc index 4100476..cf8ce96 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -1,7 +1,11 @@ ramstage-y += cstates.c -romstage-y += gpio.c
bootblock-y += early_init.c romstage-y += early_init.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +bootblock-y += variants/$(VARIANT_DIR)/superio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..bdeda72 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -68,79 +68,6 @@ device pci 1e.3 off end # AC'97 Modem device pci 1f.0 on # ISA bridge subsystemid 0x1458 0x5001 - chip superio/ite/it8718f # Super I/O - register "TMPIN1.mode" = "THERMAL_RESISTOR" - register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" - register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" - - register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = "3" - register "FAN1.smart.tmp_off" = "25" - register "FAN1.smart.tmp_start" = "30" - register "FAN1.smart.tmp_full" = "65" - register "FAN1.smart.tmp_delta" = "3" - register "FAN1.smart.smoothing" = "1" - register "FAN1.smart.pwm_start" = "0" - register "FAN1.smart.slope" = "10" - - register "FAN2.mode" = "FAN_SMART_AUTOMATIC" - register "FAN2.smart.tmpin" = "3" - register "FAN2.smart.tmp_off" = "25" - register "FAN2.smart.tmp_start" = "30" - register "FAN2.smart.tmp_full" = "65" - register "FAN2.smart.tmp_delta" = "3" - register "FAN2.smart.smoothing" = "1" - register "FAN2.smart.pwm_start" = "0" - register "FAN2.smart.slope" = "10" - - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - irq 0xf0 = 0x00 - irq 0xf1 = 0x80 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - io 0x62 = 0x000 - drq 0x74 = 4 - irq 0xf0 = 0x08 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - irq 0x70 = 0x00 - io 0x62 = 0x000 - irq 0xf0 = 0x80 - irq 0xf1 = 0x00 - irq 0xf2 = 0x0a - irq 0xf3 = 0x80 - irq 0xf4 = 0x00 - irq 0xf5 = 0x00 - irq 0xf6 = 0xff - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - irq 0x70 = 1 - io 0x62 = 0x64 - irq 0xf0 = 0x48 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - irq 0x71 = 2 - irq 0xf0 = 0 - end - end end device pci 1f.1 on # PATA/IDE subsystemid 0x1458 0xb004 diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index 4b0ea16..c204070 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -4,12 +4,7 @@ #include <device/pci_ops.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/x4x/x4x.h> -#include <superio/ite/it8718f/it8718f.h> -#include <superio/ite/common/ite.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#include <mainboard/superio.h>
/* Early mainboard specific GPIO setup. * We should use standard gpio.h eventually @@ -17,43 +12,7 @@
void bootblock_mainboard_early_init(void) { - /* Set default GPIOs on superio */ - ite_reg_write(GPIO_DEV, 0x25, 0x00); - ite_reg_write(GPIO_DEV, 0x26, 0xc7); - ite_reg_write(GPIO_DEV, 0x27, 0x80); - ite_reg_write(GPIO_DEV, 0x28, 0x41); - ite_reg_write(GPIO_DEV, 0x29, 0x0a); - ite_reg_write(GPIO_DEV, 0x2c, 0x01); - ite_reg_write(GPIO_DEV, 0x62, 0x08); - ite_reg_write(GPIO_DEV, 0x72, 0x00); - ite_reg_write(GPIO_DEV, 0x73, 0x00); - ite_reg_write(GPIO_DEV, 0xb8, 0x00); - ite_reg_write(GPIO_DEV, 0xbb, 0x40); - ite_reg_write(GPIO_DEV, 0xc0, 0x00); - ite_reg_write(GPIO_DEV, 0xc1, 0xc7); - ite_reg_write(GPIO_DEV, 0xc2, 0x80); - ite_reg_write(GPIO_DEV, 0xc3, 0x01); - ite_reg_write(GPIO_DEV, 0xc4, 0x0a); - ite_reg_write(GPIO_DEV, 0xc8, 0x00); - ite_reg_write(GPIO_DEV, 0xc9, 0x04); - ite_reg_write(GPIO_DEV, 0xcb, 0x00); - ite_reg_write(GPIO_DEV, 0xcc, 0x02); - ite_reg_write(GPIO_DEV, 0xf0, 0x10); - ite_reg_write(GPIO_DEV, 0xf1, 0x40); - ite_reg_write(GPIO_DEV, 0xf6, 0x26); - ite_reg_write(GPIO_DEV, 0xfc, 0x52); - - ite_reg_write(EC_DEV, 0xf0, 0x80); - ite_reg_write(EC_DEV, 0xf1, 0x00); - ite_reg_write(EC_DEV, 0xf2, 0x0a); - ite_reg_write(EC_DEV, 0xf3, 0x80); - ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 - ite_reg_write(EC_DEV, 0x30, 0x01); // Enable - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Disable SIO reboot */ - ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + mainboard_early_superio();
/* IRQ routing */ RCBA32(D31IP) = 0x00002210; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h b/src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h new file mode 100644 index 0000000..ddc7d04 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/include/mainboard/superio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO +#define MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO + +void mainboard_early_superio(void); + +#endif diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/superio.h b/src/mainboard/gigabyte/ga-g41m-es2l/superio.h new file mode 100644 index 0000000..62bf591 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/superio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifdef MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO +#define MAINBOARD_GIGABYTE_GA_G41M_ES2l_SUPERIO + + + +#endif diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/gpio.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-g41m-es2l/gpio.c rename to src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/gpio.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/hda_verb.c similarity index 100% rename from src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c rename to src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/hda_verb.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb new file mode 100644 index 0000000..f481195 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/overridetree.cb @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/x4x # Northbridge + device domain 0 on # PCI domain + chip southbridge/intel/i82801gx # Southbridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_DIODE" + register "TMPIN3.offset" = "0" + register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "3" + register "FAN1.smart.tmp_off" = "25" + register "FAN1.smart.tmp_start" = "30" + register "FAN1.smart.tmp_full" = "65" + register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "0" + register "FAN1.smart.slope" = "10" + + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = "3" + register "FAN2.smart.tmp_off" = "25" + register "FAN2.smart.tmp_start" = "30" + register "FAN2.smart.tmp_full" = "65" + register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.smoothing" = "1" + register "FAN2.smart.pwm_start" = "0" + register "FAN2.smart.slope" = "10" + + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x00 + irq 0xf1 = 0x80 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + io 0x62 = 0x000 + drq 0x74 = 4 + irq 0xf0 = 0x08 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0x00 + io 0x62 = 0x000 + irq 0xf0 = 0x80 + irq 0xf1 = 0x00 + irq 0xf2 = 0x0a + irq 0xf3 = 0x80 + irq 0xf4 = 0x00 + irq 0xf5 = 0x00 + irq 0xf6 = 0xff + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + irq 0xf0 = 0x48 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + irq 0x71 = 2 + irq 0xf0 = 0 + end + end + end + end + end +end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c new file mode 100644 index 0000000..c759532 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/variants/ga-g41m-es2l/superio.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <mainboard/superio.h> +#include <superio/ite/it8718f/it8718f.h> +#include <superio/ite/common/ite.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) + +void mainboard_early_superio(void) +{ + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xc7); + ite_reg_write(GPIO_DEV, 0x27, 0x80); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0xb8, 0x00); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc1, 0xc7); + ite_reg_write(GPIO_DEV, 0xc2, 0x80); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xc4, 0x0a); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x04); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xcc, 0x02); + ite_reg_write(GPIO_DEV, 0xf0, 0x10); + ite_reg_write(GPIO_DEV, 0xf1, 0x40); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x52); + + ite_reg_write(EC_DEV, 0xf0, 0x80); + ite_reg_write(EC_DEV, 0xf1, 0x00); + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); +}