Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82906?usp=email )
Change subject: mb/asrock: Add Z87M OC Formula (Haswell) ......................................................................
mb/asrock: Add Z87M OC Formula (Haswell)
This port was done via autoport and subsequent manual tweaking. Special thanks to Nicholas Chin! This port would have never succeeded without his help.
The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection switch and onboard Power and Reset switches.
Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - USB 2.0 Ports - Vertical Type A USB 2.0 - USB 3.1 Gen1 Ports - HD Audio Jack (audio output) - Front panel audio connector (audio output) - RJ-45 Gigabit LAN Port - SATA3 6.0 Gb/s connectors - mSATA/mini-PCI Express slot - half mini-PCI Express slot - PCI Express 3.0 x16 slots (both) - PCI Express 2.0 x4 slot - PCI Express 2.0 x1 slot
Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection Switch - Slow Mode Switch (locks the CPU at 800MHz)
not (yet) tested: - IR header - COM Port header - Power LED header - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - Optical SPDIF Out Port
not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. - Post Status Checker (PSC)
Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Signed-off-by: Jan Philipp Groß jeangrande@mailbox.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nicholas Chin nic.c3.14@gmail.com Reviewed-by: Felix Singer service+coreboot-gerrit@felixsinger.de --- A src/mainboard/asrock/z87m_oc_formula/Kconfig A src/mainboard/asrock/z87m_oc_formula/Kconfig.name A src/mainboard/asrock/z87m_oc_formula/Makefile.mk A src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl A src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl A src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl A src/mainboard/asrock/z87m_oc_formula/board_info.txt A src/mainboard/asrock/z87m_oc_formula/bootblock.c A src/mainboard/asrock/z87m_oc_formula/data.vbt A src/mainboard/asrock/z87m_oc_formula/devicetree.cb A src/mainboard/asrock/z87m_oc_formula/dsdt.asl A src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads A src/mainboard/asrock/z87m_oc_formula/gpio.c A src/mainboard/asrock/z87m_oc_formula/hda_verb.c A src/mainboard/asrock/z87m_oc_formula/romstage.c 15 files changed, 510 insertions(+), 0 deletions(-)
Approvals: Felix Singer: Looks good to me, approved Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig b/src/mainboard/asrock/z87m_oc_formula/Kconfig new file mode 100644 index 0000000..c05f2fd --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z87M_OC_FORMULA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87m_oc_formula" + +config MAINBOARD_PART_NUMBER + default "Z87M OC Formula" + +config USBDEBUG_HCD_INDEX + default 1 # This is the top-most of the two USB-3.0-Ports beneath the RJ45 jack. +endif diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig.name b/src/mainboard/asrock/z87m_oc_formula/Kconfig.name new file mode 100644 index 0000000..0412b1c0 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z87M_OC_FORMULA + bool "Z87M OC Formula" diff --git a/src/mainboard/asrock/z87m_oc_formula/Makefile.mk b/src/mainboard/asrock/z87m_oc_formula/Makefile.mk new file mode 100644 index 0000000..93f729d --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Makefile.mk @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_oc_formula/board_info.txt b/src/mainboard/asrock/z87m_oc_formula/board_info.txt new file mode 100644 index 0000000..072d258 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87M%20OC%20Formula/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87m_oc_formula/bootblock.c b/src/mainboard/asrock/z87m_oc_formula/bootblock.c new file mode 100644 index 0000000..1cec5c4 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/pch.h> + +/* FIXME: remove this if not needed */ +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/asrock/z87m_oc_formula/data.vbt b/src/mainboard/asrock/z87m_oc_formula/data.vbt new file mode 100644 index 0000000..0f70e00 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87m_oc_formula/devicetree.cb b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb new file mode 100644 index 0000000..cbde4cb --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_c_hotplug" = "4" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0xa" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1151 + end + device pci 1c.0 on # RP #1 + subsystemid 0x1849 0x8c10 + end + device pci 1c.1 on # RP #2 mPCIe slot + subsystemid 0x1849 0x8c12 + end + device pci 1c.2 on # RP #3 + end + device pci 1c.3 on # RP #4 PCIe NVMe Controller + end + device pci 1c.4 on # RP #5 + end + device pci 1c.5 on # RP #6 + end + device pci 1c.6 on # RP #7 + end + device pci 1c.7 on # RP #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87m_oc_formula/dsdt.asl b/src/mainboard/asrock/z87m_oc_formula/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads b/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads new file mode 100644 index 0000000..61dc90a --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI2, -- DP + HDMI3, -- HDMI + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87m_oc_formula/gpio.c b/src/mainboard/asrock/z87m_oc_formula/gpio.c new file mode 100644 index 0000000..01d39f2 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/gpio.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87m_oc_formula/hda_verb.c b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c new file mode 100644 index 0000000..ab7da86 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87m_oc_formula/romstage.c b/src/mainboard/asrock/z87m_oc_formula/romstage.c new file mode 100644 index 0000000..44932e7 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/romstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};