hannah.williams@dell.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35348 )
Change subject: Rangeley: Fix incorrect BCLK ......................................................................
Rangeley: Fix incorrect BCLK
Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR PSB_CLOCK_STS[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz.
Signed-off-by: Hannah Williams hannah.williams@dell.com Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f --- M src/cpu/intel/fsp_model_406dx/acpi.c M src/cpu/intel/fsp_model_406dx/model_406dx.h 2 files changed, 31 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35348/1
diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c index 6672eab..d6177b6 100644 --- a/src/cpu/intel/fsp_model_406dx/acpi.c +++ b/src/cpu/intel/fsp_model_406dx/acpi.c @@ -154,6 +154,33 @@ return (int)power; }
+static int get_core_frequency_mhz(int ratio) +{ + msr_t msr; + unsigned int cpu_bclk_hz[] = { + 83333333, + 100000000, + 133333333, + 116666666 + }; + int core_freq; + int index; + + /* Get BCLK - different SKUs can have different BCLK */ + msr = rdmsr(MSR_PSB_CLOCK_STS); + index = msr.lo & CPU_BCLK_MASK; + if (index >= ARRAY_SIZE(cpu_bclk_hz)) + index = 0; + + printk(BIOS_DEBUG,"MSR_PSB_CLOCK_STS %x:%x BCLK:%dHz ratio:%d\n", + msr.hi, msr.lo, cpu_bclk_hz[index], ratio); + core_freq = (cpu_bclk_hz[index] * ratio) / 1000000; + if ((cpu_bclk_hz[index] * ratio) % 1000000 > 500000) + core_freq++; + printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq); + return core_freq; +} + static void generate_P_state_entries(int core, int cores_per_package) { int ratio_min, ratio_max, ratio_turbo, ratio_step; @@ -177,7 +204,7 @@ /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * RANGELEY_BCLK; + clock_max = get_core_frequency_mhz(ratio_max);
/* Calculate CPU TDP in mW */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); @@ -240,7 +267,7 @@
/* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * RANGELEY_BCLK; + clock = get_core_frequency_mhz(ratio);
acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 53a77a9..dcfe914 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -15,8 +15,6 @@ #ifndef _CPU_INTEL_MODEL_406DX_H #define _CPU_INTEL_MODEL_406DX_H
-/* Rangeley bus clock is fixed at 100MHz */ -#define RANGELEY_BCLK 100
#define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 @@ -27,6 +25,8 @@
#define MSR_NO_EVICT_MODE 0x2e0 #define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_PSB_CLOCK_STS 0xcd +#define CPU_BCLK_MASK 0x3 #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2