[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Access conf pointer only if its not null

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30860 )

Change subject: soc/intel/cannonlake: Access conf pointer only if its not null
......................................................................

soc/intel/cannonlake: Access conf pointer only if its not null

conf pointer could be null, access it only if its not null.

Foundby=klocwork
BUG=N/A
TEST=N/A

Signed-off-by: Pratik Prajapati 
Change-Id: I1b3d6f53d2bfd9845ad7def91c4e6ca92651d216
Reviewed-on: https://review.coreboot.org/c/30860
Tested-by: build bot (Jenkins) 
Reviewed-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/cpu.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lijian Zhao: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index d0ed3ba..f987f8b 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -234,7 +234,7 @@
    config_t *conf = dev->chip_info;
    msr_t msr;

-	if (conf->speed_shift_enable) {
+	if (conf && conf->speed_shift_enable) {
    	/*
    	 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
    	 * is supported or not. coreboot needs to configure MSR 0x1AA
@@ -267,7 +267,7 @@
    msr = rdmsr(IA32_MISC_ENABLE);
    msr.lo |= (1 << 0);	/* Fast String enable */
    msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
-	if (conf->eist_enable)
+	if (conf && conf->eist_enable)
    	cpu_enable_eist();
    else
    	cpu_disable_eist();