[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/5/src/soc/intel/cannonlake/ro... 
PS5, Line 142: 	set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
> > Where's that different mechanism for NEM documented? […]

Thinking about it, setting MTRRs might have only an effect if CQOS NEM is used.
Using regular NEM the whole cache would be locked and you wont see any speed up on RAM access as there are no free cache lines.

As there's no documentation for CQOS, it's just a guess.