[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32301 )

Change subject: soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML
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Patch Set 1:
> What is the net effect of turning this on, i.e. what will FSP do
> differently for WHL today that it was not doing before?
>
> I just want to judge the risk of when to land this around an
> upcoming board build..

i could see 2 major changes with fsp running feature programming

1. C6DRAM enabling now can be done if you set EnableC6Dram UPD which was not possible earlier
2. SGX enabling, which was not possible/recommended on CNL onwards using coreboot MP init