[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add support to read SPD data from SMBus

[Ronak Kanabar (Code Review)]

Hello V Sowmya, Varshit B Pandya, build bot (Jenkins), Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39401

to look at the new patch set (#7).

Change subject: soc/intel/tigerlake: add support to read SPD data from SMBus
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soc/intel/tigerlake: add support to read SPD data from SMBus

JSLRVP has DDR4 variant which uses SMBus address to read SPD
data. So, add support to read SPD data from SMBUS.

TEST=Check compilation for jslrvp and check memory training passes.
Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/tigerlake/include/soc/meminit_jsl.h
M src/soc/intel/tigerlake/meminit_jsl.c
2 files changed, 21 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39401/7