Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39383 )
Change subject: soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries ......................................................................
soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries
If we don't pretend to have binaries, there is no need to add fake ones.
Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/ocp/tiogapass/Kconfig M src/soc/intel/xeon_sp/Kconfig 2 files changed, 1 insertion(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/39383/1
diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index dfa8f54..87e2760 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -19,7 +19,6 @@
config BOARD_SPECIFIC_OPTIONS def_bool y - select ADD_FSP_BINARIES select BOARD_ROMSIZE_KB_32768 select HAVE_ACPI_TABLES select SOC_INTEL_XEON_SP diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 8c355c4..94c0ac4 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -37,7 +37,6 @@ select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_T_XIP select FSP_M_XIP - select FSP_USE_REPO select POSTCAR_STAGE select IOAPIC select PARALLEL_MP @@ -55,6 +54,7 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS + select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
config MAINBOARD_USES_FSP2_0 @@ -69,14 +69,6 @@ select POSTCAR_CONSOLE select POSTCAR_STAGE
-# Fake FSP binary is used, as the current FSP binary for SKX-SP -# is an engineering build. It is not available to the public -# for now. -config FSP_FD_PATH - string "Location of FSP binary" - depends on FSP_USE_REPO - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0