Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36455 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... File src/soc/intel/common/block/acpi/acpi/lpc.asl:
https://review.coreboot.org/c/coreboot/+/36455/2/src/soc/intel/common/block/... PS2, Line 25: Device (DMAC)
Nice idea to have some boot BOT like of logic to ensure all CL's are getting tested.
For our common code activity we do have test rack with all possible soc 1 unit to test common CL across. if not common code then ppl do use their own unit to verify CL before pushing. But its tough to maintain common code test rack with daily code sync ensures everything works fine, i hope you could able to imagine the situation :)
It is indeed quite challenging. The idea was to eventually be able to do limited hardware (basic things like testing if it boots to the OS, ACPI resume working, ...) testing on *every* CL in gerrit. That does impose some serious speed requirements on flashing and testing.
Some automatic regression / bisection could also be implemented and posted to the mailing list.