Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8172
-gerrit
commit 7c186b21168fe8fdb367aa823ab6b23ca35bf80c Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Thu Jan 8 07:33:50 2015 +0200
ACPI: Fix S3 handoff state to ramstage
Global acpi_slp_type is now declared static. The change also guarantees it will always be initialized before.
Change-Id: I0f074bb80f06f6f0ddf4212cd8872e94ae57f949 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/x86/boot/acpi.c | 17 +++------ src/arch/x86/include/arch/acpi.h | 22 +++++------- .../intel/fsp_sandybridge/northbridge.c | 15 +++----- src/northbridge/intel/gm45/northbridge.c | 31 ++++++++-------- src/northbridge/intel/haswell/northbridge.c | 11 +++--- src/northbridge/intel/i945/northbridge.c | 17 +++------ src/northbridge/intel/nehalem/northbridge.c | 15 +++----- src/northbridge/intel/sandybridge/northbridge.c | 15 +++----- src/northbridge/intel/sch/northbridge.c | 17 +++------ src/soc/intel/baytrail/ramstage.c | 42 ++++++++++++---------- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/baytrail/xhci.c | 4 +-- src/soc/intel/broadwell/lpc.c | 4 +-- src/soc/intel/broadwell/me.c | 4 +-- src/soc/intel/broadwell/ramstage.c | 41 +++++++++++---------- src/soc/intel/broadwell/refcode.c | 11 +----- src/soc/intel/broadwell/systemagent.c | 22 ------------ src/soc/intel/fsp_baytrail/ramstage.c | 33 +++++++++-------- src/southbridge/amd/sb700/lpc.c | 17 ++++----- src/southbridge/intel/i82371eb/smbus.c | 11 ------ src/southbridge/intel/i82371eb/wakeup.c | 3 +- src/southbridge/via/vt8237r/lpc.c | 10 +++--- 22 files changed, 141 insertions(+), 223 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 61f0954..b5c22a4 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -854,22 +854,13 @@ void acpi_resume(void *wake_vec) acpi_jump_to_wakeup(wake_vec); }
-/* This is to be filled by SB code - startup value what was found. */ -u8 acpi_slp_type = 0; - -int __attribute__((weak)) acpi_get_sleep_type(void) -{ - return 0; -} +/* This is filled with acpi_is_wakeup() call early in ramstage. */ +static int acpi_slp_type = -1;
static void acpi_handoff_wakeup(void) { - static int once = 0; - if (once) - return; - - acpi_slp_type = acpi_get_sleep_type(); - once = 1; + if (acpi_slp_type < 0) + acpi_slp_type = acpi_get_sleep_type(); }
int acpi_is_wakeup(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 502c826..e748e95 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -559,14 +559,10 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest);
void acpi_save_gnvs(u32 gnvs_address);
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -/* 0 = S0, 1 = S1 ...*/ -extern u8 acpi_slp_type; - -int acpi_is_wakeup(void); -int acpi_is_wakeup_s3(void); -int acpi_is_wakeup_early(void); +/* cpu/intel/speedstep/acpi.c */ +void generate_cpu_entries(void);
+/* For ACPI S3 resume support. */ void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); void acpi_prepare_resume_backup(void); @@ -575,19 +571,19 @@ void *acpi_find_wakeup_vector(void); void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr);
+/* Returns 0 = S0, 1 = S1 ... */ int acpi_get_sleep_type(void); -#endif /* IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) */ - -/* cpu/intel/speedstep/acpi.c */ -void generate_cpu_entries(void);
static inline int acpi_s3_resume_allowed(void) { return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); }
-#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#define acpi_slp_type 0 +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +int acpi_is_wakeup(void); +int acpi_is_wakeup_s3(void); +int acpi_is_wakeup_early(void); +#else static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_early(void) { return 0; } diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index b9ecdfa..1834ced 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -329,24 +329,20 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); }
-static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } -#endif }
static struct pci_operations intel_pci_ops = { @@ -358,7 +354,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index fc54a8c..51515f4 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -220,28 +220,27 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
+int acpi_get_sleep_type(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + switch (pci_read_config32(dev, D0F0_SKPAD)) { + case SKPAD_NORMAL_BOOT_MAGIC: + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + case SKPAD_ACPI_S3_MAGIC: + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } +}
static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..498cd0b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -433,24 +433,22 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; }
-static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff;
handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
if (handoff == NULL) { printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; + return 0; } else if (handoff->s3_resume) { printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; + return 3; } else { printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; + return 0; } -#endif }
static struct pci_operations intel_pci_ops = { @@ -462,7 +460,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1aaeb3b..d4e5ef2 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -232,25 +232,21 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } }
-#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) +int acpi_get_sleep_type(void) { + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } } -#endif
static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, @@ -261,9 +257,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 2c4b1ff..21900e5 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -283,24 +283,20 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; }
-static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; + return 0; } -#endif }
static struct pci_operations intel_pci_ops = { @@ -312,7 +308,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7159700..b96ce8b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -412,24 +412,20 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; }
-static void northbridge_enable(device_t dev) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; + return 0; } -#endif }
static struct pci_operations intel_pci_ops = { @@ -441,7 +437,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index be4785e..7138ba0 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -250,25 +250,21 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } }
-#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) +int acpi_get_sleep_type(void) { + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); switch (pci_read_config32(dev, SKPAD)) { case SKPAD_NORMAL_BOOT_MAGIC: printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; + return 0; case SKPAD_ACPI_S3_MAGIC: printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; + return 3; default: printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; + return 0; } } -#endif
static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, @@ -278,9 +274,6 @@ static struct device_operations mc_ops = { .read_resources = mc_read_resources, .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..ab54049 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -130,13 +130,6 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); }
-static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - /* Save bit index for first enabled event in PM1_STS for _SB._SWS */ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { @@ -163,25 +156,36 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); }
+int acpi_get_sleep_type(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } +} + static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - - set_acpi_sleep_type(3);
- s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); }
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..f6462fa 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -215,7 +215,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); }
- if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); }
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script);
- if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return;
/* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) };
/* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..c670440 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev)
/* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); }
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..9fc6a41 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev)
static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif }
static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..38f7b5d 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -54,31 +54,36 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); }
-static inline void set_acpi_sleep_type(int val) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } }
static void s3_resume_prepare(void) { - global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; + global_nvs_t *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); - return; - } + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return;
- set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); }
void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h>
-static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret;
- if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); }
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..2e0a492 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -412,27 +412,6 @@ static void systemagent_init(struct device *dev) set_power_limits(28); }
-static void systemagent_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -451,7 +430,6 @@ static struct device_operations systemagent_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, - .enable = &systemagent_enable, .ops_pci = &broadwell_pci_ops, };
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..0b3db41 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -125,31 +125,34 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); }
- -static inline void set_acpi_sleep_type(int val) +int acpi_get_sleep_type(void) { -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } }
static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - }
- set_acpi_sleep_type(3); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); }
void baytrail_init_pre_device(void) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ebc765..658e954 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -29,7 +29,6 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> -#include <arch/acpi.h> #include <cbmem.h> #include <cpu/amd/powernow.h> #include "sb700.h" @@ -80,19 +79,15 @@ static void lpc_init(device_t dev) #endif pci_write_config8(dev, 0x78, byte);
- /* hack, but the whole sb700 startup lacks any device which - is doing the acpi init */ -#if CONFIG_HAVE_ACPI_RESUME - { - u16 tmp = inw(ACPI_PM1_CNT_BLK); - acpi_slp_type = ((tmp & (7 << 10)) >> 10); - printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); - } -#endif - cmos_check_update_date(); }
+int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + return ((tmp & (7 << 10)) >> 10); +} + void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index d236cfa..6341751 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -31,11 +31,6 @@ #include "i82371eb.h" #include "smbus.h"
-#if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; -int acpi_get_sleep_type(void); -#endif - static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -92,12 +87,6 @@ static void pwrmgt_enable(struct device *dev) outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
-#if CONFIG_HAVE_ACPI_RESUME - /* this reads PMCNTRL, so we have to call it before writing the - * default value */ - acpi_slp_type = acpi_get_sleep_type(); -#endif - /* set PMCNTRL default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index dd4a28f..f9ca385 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -19,12 +19,11 @@ */
#include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include "i82371eb.h"
-int acpi_get_sleep_type(void); - /* * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 * diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 92eaa39..d3e3d32 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -244,10 +244,6 @@ static void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); -#endif
/* All SMI on, both IDE buses ON, PSON rising edge. */ outw(0x1, VT8237R_ACPI_IO_BASE + 0x2c); @@ -258,6 +254,12 @@ static void setup_pm(device_t dev) outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); }
+int acpi_get_sleep_type(void) +{ + u16 tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} + static void vt8237r_init(struct device *dev) { u8 enables;