Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55149 )
Change subject: mb/google/guybrush: Override I2C3 pad configuration ......................................................................
mb/google/guybrush: Override I2C3 pad configuration
I2C bus to Google Security Chip (GSC) should be at 1.8V level. By default, all the I2C buses are initialized to operate at 3.3 V. Override the I2C3 pad control configuration.
BUG=b:188538373 TEST=Build and boot to OS in Guybrush. Ensure that the communication with GSC is fine.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/guybrush/Makefile.inc A src/mainboard/google/guybrush/i2c.c 2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55149/1
diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index d4eeaf5..c57b14a 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += bootblock.c +bootblock-y += i2c.c
ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin),) $(info APCB sources present.) @@ -15,6 +16,7 @@ ramstage-y += mainboard.c ramstage-y += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += i2c.c
verstage-y += verstage.c
diff --git a/src/mainboard/google/guybrush/i2c.c b/src/mainboard/google/guybrush/i2c.c new file mode 100644 index 0000000..b2ec4f2 --- /dev/null +++ b/src/mainboard/google/guybrush/i2c.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/i2c.h> +#include <soc/southbridge.h> + +#define GSC_I2C_BUS 3 + +void mainboard_i2c_override(int bus, uint32_t *pad_ctrl) +{ + if (bus != GSC_I2C_BUS) + return; + + *pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + *pad_ctrl |= I2C_PAD_CTRL_RX_SEL_1_8V; +}