Attention is currently required from: Angel Pons, Arthur Heymans, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55238 )
Change subject: [WIP,RFC] sb,soc/intel: Remove option power_on_after_fail from SMI ......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55238/comment/9d4aa0db_91f7ffcb PS1, Line 9: The mechanism was flawed. In the case that nvram contents were
This write is done to emulate the "keep" setting, as the hardware only knows "on" and "off".
I know. To have an NVS bit is a less bad choice than CMOS or SMBUS+EEPROM. But NVS store is outside TSEG.
If I remember correctly, we link (static) devicetree into SMM now for chip_info access and that is something that should be fixed too. There is a general need for passing some configuration bits to SMI handlers, something to put into SMM module loader probably.