[coreboot-gerrit] Change in coreboot[master]: soc/intel/{apl,cnl,icl,skl,tgl}: Update SA bit fields as per EDS

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38387 )

Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Update SA bit fields as per EDS
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Patch Set 10:

(4 comments)

https://review.coreboot.org/c/coreboot/+/38387/5/src/soc/intel/common/block/... 
File src/soc/intel/common/block/acpi/acpi/northbridge.asl:

https://review.coreboot.org/c/coreboot/+/38387/5/src/soc/intel/common/block/... 
PS5, Line 39: 38:16
> send you register details

Ack

https://review.coreboot.org/c/coreboot/+/38387/5/src/soc/intel/common/block/... 
PS5, Line 43: PXSZ, 2,
> send you register details

Ack

https://review.coreboot.org/c/coreboot/+/38387/5/src/soc/intel/common/block/... 
PS5, Line 45: 38:28
> all PCIE BAR is 28:38 except APL/GLK

Ack

https://review.coreboot.org/c/coreboot/+/38387/5/src/soc/intel/common/block/... 
PS5, Line 223: 16
> this is correct as per my observation

Ack