Attention is currently required from: Tim Wawrzynczak, Wisley Chen, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58878 )
Change subject: soc/intel/alderlake: Enable Intel FIVR RFI settings ......................................................................
Patch Set 1:
(3 comments)
File src/soc/intel/alderlake/chip.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132130): https://review.coreboot.org/c/coreboot/+/58878/comment/e5221d19_2ba08940 PS1, Line 510: * Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Range is translated to an encoded value for FIVR register. line over 96 characters
File src/soc/intel/alderlake/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132130): https://review.coreboot.org/c/coreboot/+/58878/comment/b6c63722_a6634aa4 PS1, Line 735: const struct soc_intel_alderlake_config *config) code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-132130): https://review.coreboot.org/c/coreboot/+/58878/comment/6940e128_345eadbc PS1, Line 735: const struct soc_intel_alderlake_config *config) please, no spaces at the start of a line