Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38994 )
Change subject: soc/intel/xeon_sp: Enable LPC generic IO decode range ......................................................................
soc/intel/xeon_sp: Enable LPC generic IO decode range
To use Intel common block LPC function that enables the IO ranges defined in devicetree.cb.
Tested on OCP Tioga Pass with BMC LPC working. Signed-off-by: Johnny Lin johnny_lin@wiwynn.com
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8 --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/bootblock/pch.c M src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/include/soc/bootblock.h M src/soc/intel/xeon_sp/lpc.c 6 files changed, 80 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/38994/1
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index c4db44c..3e7dadb 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -26,6 +26,8 @@ subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/pch.c +bootblock-y += lpc.c bootblock-y += spi.c
postcar-y += soc_util.c diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 15435fa..835f03c 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <intelblocks/rtc.h> #include <intelblocks/fast_spi.h> #include <soc/iomap.h> +#include <soc/bootblock.h> #include <spi-generic.h> #include <timestamp.h> #include <console/console.h> @@ -55,6 +56,7 @@ void bootblock_soc_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); + pch_early_iorange_init(); }
void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/bootblock/pch.c b/src/soc/intel/xeon_sp/bootblock/pch.c new file mode 100644 index 0000000..6b7b27d --- /dev/null +++ b/src/soc/intel/xeon_sp/bootblock/pch.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2019 Intel Corporation. + * Copyright (C) 2020 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/lpc_lib.h> +#include <soc/bootblock.h> + +void pch_early_iorange_init(void) +{ + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h index 046c746..fda6498 100644 --- a/src/soc/intel/xeon_sp/chip.h +++ b/src/soc/intel/xeon_sp/chip.h @@ -82,6 +82,12 @@ uint32_t vtd_support; uint32_t coherency_support; uint32_t ats_support; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; };
extern struct chip_operations soc_intel_xeon_sp_ops; diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h new file mode 100644 index 0000000..77f3516 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2020 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOOTBLOCK_H_ +#define _SOC_BOOTBLOCK_H_ + +void pch_early_iorange_init(void); + +#endif diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index d4e5d9d..0bd81b4 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -18,8 +18,12 @@ #include <console/console.h> #include <arch/ioapic.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> #include <soc/soc_util.h> #include <soc/iomap.h> +#include <soc/pcr_ids.h> + +#include "chip.h"
static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { { 0, 0 } @@ -30,6 +34,25 @@ return xeon_lpc_fixed_mmio_ranges; }
+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + void lpc_soc_init(struct device *dev) { printk(BIOS_SPEW, "pch: lpc_init\n");