[coreboot-gerrit] Change in coreboot[master]: cpu/intel/common/fsb.c: add Crystal Well support

[Iru Cai (vimacs) (Code Review)]

Hello Iru Cai,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44065

to review the following change.

Change subject: cpu/intel/common/fsb.c: add Crystal Well support
......................................................................

cpu/intel/common/fsb.c: add Crystal Well support

Without this change, there will be no console output when using a
Crystal Well CPU.

Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS.

Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9
Signed-off-by: Iru Cai 
---
M src/cpu/intel/common/fsb.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44065/1

diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 7772171..3d46bbc 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -45,6 +45,7 @@
    	case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
    	case 0x3c: /* Haswell BCLK fixed at 100MHz */
    	case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
+		case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */
    		*fsb = 100;
    		*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
    		break;