[coreboot-gerrit] Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Tim Crawford, SRIDHAR SIRICILLA, Furquan Shaikh, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Sridhar Siricilla, Arthur Heymans, Evgeny Zinoviev, Patrick Rudolph.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 )

Change subject: soc/intel: Allow enable/disable ME via CMOS
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Patch Set 75:

(2 comments)

File src/soc/intel/common/block/cse/cse.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129753):
https://review.coreboot.org/c/coreboot/+/52800/comment/e73ac3b3_01c5c989 
PS75, Line 1039:   
trailing whitespace

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-129753):
https://review.coreboot.org/c/coreboot/+/52800/comment/cd404564_7e0c0c59 
PS75, Line 1039:   
please, no spaces at the start of a line