[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR

[Shuo Liu (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Tim Chu.

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email )

Change subject: soc/intel/xeon_sp: Reserve PRMRR
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Patch Set 6:

(1 comment)

File src/include/cpu/x86/mtrr.h:

https://review.coreboot.org/c/coreboot/+/84314/comment/c9a3378c_d2e10f10?usp... :
PS6, Line 171: /*
             :  * fls64: find least significant bit set in a 64-bit word
             :  * As samples, fls64(0x0) = 64; fls64(0x4400) = 10;
             :  * fls64(0x40400000000) = 34.
             :  */
             : static uint32_t fls64(uint64_t x)
             : {
             : 	uint32_t lo = (uint32_t)x;
             : 	if (lo)
             : 		return fls(lo);
             : 	uint32_t hi = x >> 32;
             : 	return fls(hi) + 32;
             : }
> https://github.com/coreboot/coreboot/blob/2dd8f2e13b9e8bf10cd98e707534975f9e.... […]

Agree, the lib.h implementation is more generic. So I will ack this first and add another patch upon this one.