[coreboot-gerrit] Change in coreboot[master]: intel/i440bx: Resolve long standing raminit TODOs

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38383 )

Change subject: intel/i440bx: Resolve long standing raminit TODOs
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intel/i440bx: Resolve long standing raminit TODOs

Drop DRAMT write as it's only rewriting the power on default.

PMCR write is required. Update comment on its purpose and move to
end of sdram_enable().

Change-Id: I62e8b2531f0f297ffb7db440db89ffa65771b7d5
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38383
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/northbridge/intel/i440bx/raminit.c
1 file changed, 2 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index d5c23cf..0a864e8 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -357,10 +357,7 @@
     *         1 = Enable
     *         0 = Disable
     */
-	/* Enable normal refresh and the gated clock. */
-	// TODO: Only do this later?
-	// PMCR, 0x00, 0x14,
-	PMCR, 0x00, 0x00,
+	/* PMCR will be set later. */

/* Enable SCRR.SRRAEN and let BX choose the SRR. */
    SCRR + 1, 0x00, 0x10,
@@ -985,13 +982,6 @@

/* Setup DRAM buffer strength. */
    set_dram_buffer_strength();
-
-	/* TODO: Set PMCR? */
-	// pci_write_config8(NB, PMCR, 0x14);
-	pci_write_config8(NB, PMCR, 0x10);
-
-	/* TODO: This is for EDO memory only. */
-	pci_write_config8(NB, DRAMT, 0x03);
 }

static void sdram_enable(void)
@@ -1030,7 +1020,7 @@

/* 6. Finally enable refresh. */
    PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
-	// pci_write_config8(NB, PMCR, 0x10);
+	pci_write_config8(NB, PMCR, 0x10);
    spd_enable_refresh();
    udelay(1);