Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82719?usp=email )
Change subject: mb/google/trulo/var/orisa: Enable HDA Codec ALC256 ......................................................................
mb/google/trulo/var/orisa: Enable HDA Codec ALC256
We use ALC256 as HDA codec on orisa. Add verb table and the related device tree changes for HDA related registers.
BUG=b:338523452 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot
Change-Id: I92051886341bd317cce6061ece83439d156b0f90 Signed-off-by: Amanda Huang amanda_hwang@compal.corp-partner.google.com --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/orisa/Makefile.mk A src/mainboard/google/brya/variants/orisa/hda_verb.c M src/mainboard/google/brya/variants/orisa/overridetree.cb 4 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/82719/1
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9f6a026..5697052 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -374,6 +374,7 @@
config BOARD_GOOGLE_ORISA select BOARD_GOOGLE_BASEBOARD_TRULO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB
config BOARD_GOOGLE_OSIRIS select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/orisa/Makefile.mk b/src/mainboard/google/brya/variants/orisa/Makefile.mk index 91f031e..0bc6c14 100644 --- a/src/mainboard/google/brya/variants/orisa/Makefile.mk +++ b/src/mainboard/google/brya/variants/orisa/Makefile.mk @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c + romstage-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/orisa/hda_verb.c b/src/mainboard/google/brya/variants/orisa/hda_verb.c new file mode 100644 index 0000000..bf998e1 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/hda_verb.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0x10ec12ac, // Subsystem ID + 0x00000013, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting - 1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default (used for headset) + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 0d20a3a..42e31f4 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -91,6 +91,15 @@ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. register "tcss_aux_ori" = "0"
+ # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_sdi_enable[1]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + # Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, @@ -520,5 +529,13 @@ end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end