[coreboot-gerrit] [S] Change in coreboot[main]: arch/riscv: minimal changes to get sifive unmatched with non-SMP

[ron minnich (Code Review)]

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81308?usp=email )

Change subject: arch/riscv: minimal changes to get sifive unmatched with non-SMP
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arch/riscv: minimal changes to get sifive unmatched with non-SMP

Change-Id: I2ac227e5b2833758506c8d0a8f6ac743ee226d58
Signed-off-by: Ronald G Minnich 
---
M src/arch/riscv/payload.c
1 file changed, 14 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/81308/1

diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 636462f..fd6fd3d 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <cbmem.h>
+#include <delay.h>
 #include <program_loading.h>
 #include <stdint.h>
 #include <arch/boot.h>
@@ -41,11 +42,16 @@
    void (*doit)(int hart_id, void *fdt) = prog_entry(prog);
    int hart_id = read_csr(mhartid);
    uintptr_t status = read_csr(mstatus);
-	extern void *_text, *_estack;
+	extern char _text[], _estack[];
    status = INSERT_FIELD(status, MSTATUS_MPIE, 0);

+	for (; hart_id != CONFIG_RISCV_WORKING_HARTID;) {
+		mdelay(1000 * hart_id + 1000);
+	}
+
    switch (payload_mode) {
    case RISCV_PAYLOAD_MODE_S:
+		mstatus_init();
    	/*
    	 * Set up a PMP to protect coreboot, then close the PMPs.
    	 * If a mainboard or SoC needs other ranges
@@ -61,8 +67,9 @@
    	 * small, make this an NAPOT area. The linker scripts
    	 * should round _text and _estack to 4K.
    	 */
+		printk(BIOS_DEBUG, "setup %p %p PMP_R\n", _text, _estack);
    	setup_pmp((u64)(uintptr_t) _text,
-				(u64)(uintptr_t) _estack - (u64)(uintptr_t) _text, 0);
+				(u64)(uintptr_t) _estack - (u64)(uintptr_t) _text, PMP_R);

/*
    	 * All pmp operations should be finished when close_pmp is called.
@@ -82,6 +89,9 @@
    	write_csr(satp, 0);
    	/* save stack to mscratch so trap_entry can use that as exception stack */
    	write_csr(mscratch, MACHINE_STACK_TOP());
+		/* disable M-Mode interrupt */
+		write_csr(mie, 0);
+
    	break;
    case RISCV_PAYLOAD_MODE_M:
    	status = INSERT_FIELD(status, MSTATUS_MPP, PRV_M);
@@ -94,8 +104,10 @@
    	die("wrong privilege level for payload");
    	break;
    }
+	printk(BIOS_DEBUG, "%s(%p, %p) mstatus: 0x%lx\n", __func__, doit, fdt, status);
    write_csr(mstatus, status);
    write_csr(mepc, doit);
+	printk(BIOS_DEBUG, "GO!\n");
    asm volatile(
    	"mv a0, %0\n\t"
    	"mv a1, %1\n\t"