[coreboot-gerrit] Change in coreboot[master]: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35722

to look at the new patch set (#3).

Change subject: [TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR
......................................................................

[TEST,NOTFORMERGE]cpu/intel/car: Test setting XIP CACHE during CAR

Totest: Does it still boot? Are romstage timestamps affected (does
caching work)?

It does work and the CR0 bits don't even seem necessary.

Change-Id: I424e3804442b823880f89dcee9d1478cebb55bde
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/car/romstage.c
A src/cpu/intel/car/set_mtrr.S
A src/cpu/intel/car/set_mtrr.h
M src/cpu/intel/socket_LGA775/Makefile.inc
5 files changed, 108 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35722/3