[coreboot-gerrit] Change in coreboot[master]: soc/intel: Memory config changes for Deltan

[Varun Joshi (Code Review)]

Hello Varun Joshi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/39847

to review the following change.

Change subject: soc/intel: Memory config changes for Deltan
......................................................................

soc/intel: Memory config changes for Deltan

SODIMM Specific memory configuration

Signed-off-by: Varun Joshi 
Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
M src/soc/intel/tigerlake/meminit_tgl.c
2 files changed, 69 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/39847/1

diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
index 5573fb7..b4fbfe5 100644
--- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
@@ -13,6 +13,7 @@
 #include <fsp/soc_binding.h>

#define BYTES_PER_CHANNEL	2
+#define NUM_DIMM_SLOT		2
 #define BITS_PER_BYTE		8
 #define DQS_PER_CHANNEL		2
 #define NUM_CHANNELS		8
@@ -24,6 +25,7 @@

enum mem_info_read_type {
    NOT_EXISTING,	/* No memory in this channel */
+	READ_SMBUS,	/* Read on-module spd by SMBUS. */
    READ_SPD_CBFS,	/* Find spd file in CBFS. */
    READ_SPD_MEMPTR	/* Find spd data from pointer. */
 };
@@ -31,6 +33,8 @@
 struct spd_info {
    enum mem_info_read_type read_type;
    union spd_data_by {
+		/* To read on-module spd when read_type is READ_SMBUS. */
+		uint8_t spd_smbus_address;
    	/* To identify spd file when read_type is READ_SPD_CBFS. */
    	int spd_index;

@@ -41,6 +45,8 @@

/* Board-specific memory configuration information */
 struct mb_lpddr4x_cfg {
+	/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
+	struct spd_info spd[NUM_DIMM_SLOT];
    /* DQ mapping */
    uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE];

@@ -52,7 +58,24 @@
     * pin on the CPU that DRAM pin connects to.
     */
    uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL];
-
+	/*
+	 * Rcomp resistor value. The value represent the resistance in
+	 * ohms of the rcomp resistor attached to the DDR_COMP pins on the DRAM.
+	 */
+	uint16_t rcomp_resistor;
+	/*
+	 * Indicates whether memory is interleaved.
+	 * Set to 1 for an interleaved design,
+	 * set to 0 for non-interleaved design.
+	 */
+	uint8_t dq_pins_interleaved;
+	/*
+	 * VREF_CA configuration.
+	 * Set to 0 VREF_CA goes to both CH_A and CH_B,
+	 * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
+	 * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
+	 */
+	uint8_t vref_ca_config;
    /*
     * Early Command Training Enable/Disable Control
     * 1 = enable, 0 = disable
@@ -60,6 +83,10 @@
    uint8_t ect;
 };

+/* Initialize default memory configurations for TigerLake */
+void tigerlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
+			   const struct  mb_lpddr4x_cfg *tgl_cfg);
+
 /* Initialize default memory configurations for dimm0-only lpddr4x */
 void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg,
    		   const struct mb_lpddr4x_cfg *board_cfg,
diff --git a/src/soc/intel/tigerlake/meminit_tgl.c b/src/soc/intel/tigerlake/meminit_tgl.c
index a0e5107..2d01cc2 100644
--- a/src/soc/intel/tigerlake/meminit_tgl.c
+++ b/src/soc/intel/tigerlake/meminit_tgl.c
@@ -25,7 +25,7 @@
    	       &_b_cfg->dq_map[_ch],			\
    		sizeof(_b_cfg->dq_map[_ch]));		\
    	memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch,	\
-			&_b_cfg->dqs_map[_ch],			\
+		       &_b_cfg->dqs_map[_ch],			\
    		sizeof(_b_cfg->dqs_map[_ch]));		\
    } while (0)

@@ -161,3 +161,43 @@
    mem_cfg->ECT = board_cfg->ect;
    mem_cfg->MrcSafeConfig = 0x1;
 }
+static void meminit_memcfg(FSP_M_CONFIG *mem_cfg,
+			   const struct mb_lpddr4x_cfg *board_cfg)
+{
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0);
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1);
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2);
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3);
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4);
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5);
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6);
+	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7);
+}
+
+/* Initialize onboard memory configurations for TigerLake */
+void tigerlake_memcfg_init(FSP_M_CONFIG *mem_cfg,
+			   const struct mb_lpddr4x_cfg *board_cfg)
+{
+	const struct spd_info *spdi;
+
+	/* Early Command Training Enabled */
+	mem_cfg->ECT = board_cfg->ect;
+	mem_cfg->RcompResistor = board_cfg->rcomp_resistor;
+	mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved;
+
+	for (int i = 0; i < NUM_DIMM_SLOT; i++) {
+		spdi = &(board_cfg->spd[i]);
+		switch (spdi->read_type) {
+			case NOT_EXISTING:
+				break;
+			case READ_SMBUS:
+				mem_cfg->SpdAddressTable[i] =
+					spdi->spd_spec.spd_smbus_address;
+				break;
+			default:
+				die("no valid way to read mem info");
+		}
+
+		meminit_memcfg(mem_cfg, board_cfg);
+	}
+}