[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Enable SATA ports

[Andrey Petrov (Code Review)]

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39918 )

Change subject: soc/intel/xeon_sp/cpx: Enable SATA ports
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soc/intel/xeon_sp/cpx: Enable SATA ports

Looks like FSP does not explicity configure SATA ports as enabled.
As result some payloads (SeaBIOS, TianoCore) can detect the drives
but Linux kernel does not. Turns out the kernel does not touch
disabled ports, while SeaBIOS just checks all available ports.
Interestingly, SKX FSP seems to be enabling all the ports.

This change hooks up some common SATA code which enables all ports.

TEST=booted on Cedar Island CRB, make sure 7-pin SATA drive works

Change-Id: Iba8f8c8812168deace1abaa7cf3996b870648686
---
M src/soc/intel/xeon_sp/cpx/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/39918/1

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 70703d0..2f637b1 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -17,6 +17,8 @@
      select POSTCAR_CONSOLE
      select POSTCAR_STAGE
      select FSP_USES_CB_STACK
+	  select SOC_INTEL_COMMON_BLOCK_SATA
+	  select SOC_AHCI_PORT_IMPLEMENTED_INVERT

config FSP_HEADER_PATH
      string "Location of FSP headers"