Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48006 )
Change subject: soc/intel/skylake: Align memcpys for better readability ......................................................................
soc/intel/skylake: Align memcpys for better readability
Change-Id: I54bac053555e636d51678299d748fe7420d055dd Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/soc/intel/skylake/chip.c 1 file changed, 11 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48006/1
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index e2aee07..77ff78b 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -177,13 +177,13 @@ params->SataEnable = dev && dev->enabled; if (params->SataEnable) { memcpy(params->SataPortsEnable, config->SataPortsEnable, - sizeof(params->SataPortsEnable)); + sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, - sizeof(params->SataPortsDevSlp)); + sizeof(params->SataPortsDevSlp)); memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, - sizeof(params->SataPortsHotPlug)); + sizeof(params->SataPortsHotPlug)); memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, - sizeof(params->SataPortsSpinUp)); + sizeof(params->SataPortsSpinUp));
params->SataSalpSupport = config->SataSalpSupport; params->SataMode = config->SataMode; @@ -198,16 +198,15 @@ }
memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, - sizeof(params->PcieRpClkReqSupport)); + sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, - sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpAdvancedErrorReporting, - config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + sizeof(params->PcieRpClkReqNumber)); + memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, + sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, - sizeof(params->PcieRpLtrEnable)); + sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + sizeof(params->PcieRpHotPlug)); for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; if (config->pcie_rp_aspm[i]) @@ -238,7 +237,7 @@ params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
memcpy(params->SerialIoDevMode, config->SerialIoDevMode, - sizeof(params->SerialIoDevMode)); + sizeof(params->SerialIoDevMode));
dev = pcidev_path_on_root(PCH_DEVFN_CIO); params->PchCio2Enable = dev && dev->enabled;