[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: Override GPIO PM configuration

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45857 )

Change subject: mb/google/dedede: Override GPIO PM configuration
......................................................................

mb/google/dedede: Override GPIO PM configuration

If Cr50 is running old firmware version and hence does not ensure long
interrupt pulses, override the GPIO PM configuration.

BUG=None
TEST=Build and boot waddledee to OS. Ensure that the suspend/resume
sequence works fine.

Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/mainboard/google/dedede/mainboard.c
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
2 files changed, 20 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/45857/1

diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c
index cb84e1f..150076f 100644
--- a/src/mainboard/google/dedede/mainboard.c
+++ b/src/mainboard/google/dedede/mainboard.c
@@ -4,9 +4,29 @@
 #include <bootstate.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
+#include <drivers/spi/tpm/tpm.h>
 #include <ec/ec.h>
+#include <security/tpm/tss.h>
+#include <soc/ramstage.h>
 #include <vendorcode/google/chromeos/chromeos.h>

+void mainboard_update_soc_chip_config(struct soc_intel_jasperlake_config *cfg)
+{
+	int ret;
+	ret = tlcl_lib_init();
+	if (ret != VB2_SUCCESS) {
+		printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
+		return;
+	}
+
+	if (!cr50_is_long_interrupt_pulse_enabled()) {
+		/* Disable GPIO PM to allow for shorter IRQ pulses */
+		printk(BIOS_INFO, "Override GPIO PM\n");
+		cfg->gpio_override_pm = 1;
+		memset(cfg->gpio_pm, 0, sizeof(cfg->gpio_pm));
+	}
+}
+
 __weak void variant_isst_override(void)
 {
    /*
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 1f72eb1..3ced742 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -129,14 +129,6 @@
    # Select eDP for port A
    register "DdiPortAConfig" = "1"

-	# Disable PM to allow for shorter irq pulses
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[0]" = "0"
-	register "gpio_pm[1]" = "0"
-	register "gpio_pm[2]" = "0"
-	register "gpio_pm[3]" = "0"
-	register "gpio_pm[4]" = "0"
-
    # Enable HPD for DDI ports B/C
    register "DdiPortBHpd" = "1"
    register "DdiPortCHpd" = "1"