Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Angel Pons, Aamir Bohra, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41674
to look at the new patch set (#4).
Change subject: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7 ......................................................................
soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7
This patch ensures SATA PCI config space offset 0x92 (SPD) is written correctly based on MMIO offset 0x0c (GHC_PI)
PCH-H platform has more than 3 SATA port hence observed this issue when SATA device is connected at Port > 3.
Without this CL : GHC_PI = 0x0F (Port 0-3 enable) Value written into SPD = 0xFF (Assume SPD read returns 0xFF) Results = All SATA Ports are disabled
With this CL : GHC_PI = 0x0F (Port 0-3 enable) Value written into SPD = 0xF0 Results = Port 0-3 are enable and 4-7 are disabled.
TEST=Able to detect SATA device connect at Port 4 on CML-H.
Change-Id: Ied3832b26ba1fdd4c30fafe8149689a01d302c3e Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/sata/sata.c 1 file changed, 2 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/41674/4