Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/25547
Change subject: soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common location ......................................................................
soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common location
Move flush_l1d_l2 function to common location within the SoC.
BUG=None: BRANCH=None TEST= Build for glkrvp.
Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141 Signed-off-by: Naresh G Solanki naresh.solanki@intel.com --- M src/soc/intel/apollolake/car.c M src/soc/intel/apollolake/include/soc/cpu.h 2 files changed, 11 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/25547/1
diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index f46e0f8..920580d 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -20,19 +20,13 @@ #include <cpu/x86/msr.h> #include <intelblocks/msr.h> #include <program_loading.h> +#include <soc/cpu.h>
/* * This file supports the necessary hoops one needs to jump through since * early FSP component and early stages are running from cache-as-ram. */
-static void flush_l1d_to_l2(void) -{ - msr_t msr = rdmsr(MSR_POWER_MISC); - msr.lo |= FLUSH_DL1_L2; - wrmsr(MSR_POWER_MISC, msr); -} - static inline int is_car_addr(uintptr_t addr) { return ((addr >= CONFIG_DCACHE_RAM_BASE) && diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index ed4a7de..4a1a7a4 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -18,6 +18,9 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_
+#include <cpu/x86/msr.h> +#include <intelblocks/msr.h> + /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000
@@ -25,4 +28,11 @@ void apollolake_init_cpus(struct device *dev); void mainboard_devtree_update(struct device *dev);
+/* Flush L1D to L2 */ +static inline void flush_l1d_to_l2(void) +{ + msr_t msr = rdmsr(MSR_POWER_MISC); + msr.lo |= FLUSH_DL1_L2; + wrmsr(MSR_POWER_MISC, msr); +} #endif /* _SOC_APOLLOLAKE_CPU_H_ */