Attention is currently required from: Keith Hui.
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73690
to look at the new patch set (#5).
Change subject: nb/intel/snb: Normalize spd_addresses in devicetree ......................................................................
nb/intel/snb: Normalize spd_addresses in devicetree
DIMM SPD addresses are listed in coreboot as their actual SMBus addresses (i.e. 0x50-0x53) while MRC raminit expects them as passed through pei_data structure to be shifted left 1 bit because that's what the underlying Intel SMBus controller expects. This change adds code to translate between devicetree and pei_data, and prepares this setting to be applied to native raminit as well.
Commit 5709e03613b3 ("nb/intel/sandybridge: Migrate MRC settings to devicetree") introduced devicetree settings to declare SPD addresses in May 2019, but as of time of writing no board uses this mechanism, so now is the time to correct it.
Update comments in nb/intel/snb/chip.h as well.
Change-Id: Ie5604daec167bcf15ad58fa4032b2c6d233e5448 Signed-off-by: Keith Hui buurin@gmail.com --- M src/northbridge/intel/sandybridge/chip.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 34 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/73690/5