[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/braswell/smbus.c: Add support for i2c mode block write

[Frans Hendriks (Code Review)]

Hello Patrick Rudolph, Arthur Heymans, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Nico Huber,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33225

to look at the new patch set (#5).

Change subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write
......................................................................

soc/intel/braswell/smbus.c: Add support for i2c mode block write

Intel Braswell supports i2c block write using SMBus controller.

smbus_i2c_block_write() is added to configure SMBus controller in I2C mode
before calling do_smbus_block_write().
i2c clients expect first byte after i2c slave address is register address[16:8].
The SMBus controlller put the slave address on the bus followed by the value in
SMBHSTDAT1. smbus_i2c_block_write() will fill the SMBHSTDAT1 register before
executing do_smbus_block_write().

Add smbus.c to ramstage.

BUG=N/A
TEST=Config eDP for LCD display on Facebook FBG-1701

Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a
Signed-off-by: Frans Hendriks 
---
A src/soc/intel/braswell/include/soc/smbus.h
M src/soc/intel/braswell/smbus.c
2 files changed, 61 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33225/5