[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46731 )

Change subject: soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`
......................................................................

soc/intel/broadwell/cpu.c: Re-add `configure_thermal_target`

This is needed because a follow-up removes Intel common SoC code Kconfig
options. This will eventually be deduplicated once merged with Haswell.

Tested on out-of-tree Acer E5-573, still boots.

Change-Id: Ib7ab4e75bd4416dde4612e67405a871da569008a
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/cpu.c
1 file changed, 23 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46731/1

diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 00460c6..694c727 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -290,6 +290,28 @@
    wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }

+static void configure_thermal_target(void)
+{
+	config_t *conf;
+	struct device *lapic;
+	msr_t msr;
+
+	/* Find pointer to CPU configuration */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic || !lapic->chip_info)
+		return;
+	conf = lapic->chip_info;
+
+	/* Set TCC activation offset if supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
+	}
+}
+
 static void configure_misc(void)
 {
    msr_t msr;
@@ -372,7 +394,7 @@
    configure_misc();

/* Thermal throttle activation offset */
-	configure_tcc_thermal_target();
+	configure_thermal_target();

/* Enable Direct Cache Access */
    configure_dca_cap();