Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16318
-gerrit
commit aee5b0e7ed95b6c9b886099b4e4ef760316c3fe8 Author: Aaron Durbin adurbin@chromium.org Date: Wed Aug 24 14:58:12 2016 -0500
vboot: consolidate google_chromeec_early_init() calls
On x86 platforms, google_chromeec_early_init() is used to put the EC into RO mode when there's a recovery request. This is to avoid training memory multiple times when the recovery request is through an EC host event while the EC is running RW code. Under that condition the EC will be reset (along with the rest of the system) when the kernel verification happens. This leads to an execessively long recovery path because of the double reboot performing full memory training each time.
By putting this logic into the verstage program this reduces the bootblock size on the skylake boards. Additionally, this provides the the correct logic for all future boards since it's not tied to FSP nor the mainboard itself. Lastly, this double memory training protection works only for platforms which verify starting from bootblock. The platforms which don't start verifying until after romstage need to have their own calls (such as haswell and baytrail).
Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/drivers/intel/fsp1_1/car.c | 6 ------ src/drivers/intel/fsp2_0/memory_init.c | 9 --------- src/mainboard/google/chell/bootblock_mainboard.c | 4 ---- src/mainboard/google/glados/bootblock_mainboard.c | 4 ---- src/mainboard/google/lars/bootblock_mainboard.c | 4 ---- src/mainboard/intel/kunimitsu/bootblock_mainboard.c | 4 ---- src/vboot/vboot_loader.c | 21 +++++++++++++++++++++ 7 files changed, 21 insertions(+), 31 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 7eceebf..1a5f9a8 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -15,7 +15,6 @@
#include <arch/early_variables.h> #include <console/console.h> -#include <ec/google/chromeec/ec.h> #include <fsp/car.h> #include <fsp/util.h> #include <program_loading.h> @@ -62,11 +61,6 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params) car_soc_post_console_init(); car_mainboard_post_console_init();
- /* Ensure the EC is in the right mode for recovery */ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) && - !IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) - google_chromeec_early_init(); - set_fih_car(car_params->fih);
/* Return new stack value in RAM back to assembly stub. */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index e545b6d..1957cdb 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -17,7 +17,6 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <ec/google/chromeec/ec.h> #include <elog.h> #include <fsp/api.h> #include <fsp/util.h> @@ -296,14 +295,6 @@ void fsp_memory_init(bool s3wake) if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) boot_count_increment();
- /* - * Before doing any memory init/training, ensure that the EC is in the - * right mode. This saves an additional memory training when in recovery - * mode. - */ - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) - google_chromeec_early_init(); - if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); die("FSPM not available!\n"); diff --git a/src/mainboard/google/chell/bootblock_mainboard.c b/src/mainboard/google/chell/bootblock_mainboard.c index d514622..627b4e8 100644 --- a/src/mainboard/google/chell/bootblock_mainboard.c +++ b/src/mainboard/google/chell/bootblock_mainboard.c @@ -14,7 +14,6 @@ */
#include <bootblock_common.h> -#include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - early_config_gpio(); } diff --git a/src/mainboard/google/glados/bootblock_mainboard.c b/src/mainboard/google/glados/bootblock_mainboard.c index d514622..627b4e8 100644 --- a/src/mainboard/google/glados/bootblock_mainboard.c +++ b/src/mainboard/google/glados/bootblock_mainboard.c @@ -14,7 +14,6 @@ */
#include <bootblock_common.h> -#include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - early_config_gpio(); } diff --git a/src/mainboard/google/lars/bootblock_mainboard.c b/src/mainboard/google/lars/bootblock_mainboard.c index d514622..627b4e8 100644 --- a/src/mainboard/google/lars/bootblock_mainboard.c +++ b/src/mainboard/google/lars/bootblock_mainboard.c @@ -14,7 +14,6 @@ */
#include <bootblock_common.h> -#include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - early_config_gpio(); } diff --git a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c index d514622..627b4e8 100644 --- a/src/mainboard/intel/kunimitsu/bootblock_mainboard.c +++ b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c @@ -14,7 +14,6 @@ */
#include <bootblock_common.h> -#include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include "gpio.h"
@@ -28,8 +27,5 @@ static void early_config_gpio(void)
void bootblock_mainboard_init(void) { - /* Ensure the EC and PD are in the right mode for recovery */ - google_chromeec_early_init(); - early_config_gpio(); } diff --git a/src/vboot/vboot_loader.c b/src/vboot/vboot_loader.c index 7395fd7..207aada 100644 --- a/src/vboot/vboot_loader.c +++ b/src/vboot/vboot_loader.c @@ -17,6 +17,7 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <ec/google/chromeec/ec.h> #include <rmodule.h> #include <rules.h> #include <string.h> @@ -89,9 +90,29 @@ int vb2_logic_executed(void) static void vboot_prepare(void) { if (verification_should_run()) { + /* + * Note that this path isn't taken when + * CONFIG_RETURN_FROM_VERSTAGE is employed. + */ verstage_main(); car_set_var(vboot_executed, 1); vb2_save_recovery_reason_vbnv(); + + /* + * Avoid double memory retrain when the EC is running RW code + * and a recovery request came in through an EC host event. The + * double retrain happens because the EC won't be rebooted + * until kernel verification notices the EC isn't running RO + * code which is after memory training. Therefore, reboot the + * EC after we've saved the potential recovery request so it's + * not lost. Lastly, only perform this sequence on x86 + * platforms since those are the ones that currently do a + * costly memory training in recovery mode. + */ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) && + IS_ENABLED(CONFIG_ARCH_X86)) + google_chromeec_early_init(); + } else if (verstage_should_load()) { struct cbfsf file; struct prog verstage =