Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43760 )
Change subject: mb/clevo/kbl-u: Add Clevo N240BU as variant ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43760/25/src/mainboard/clevo/kbl-u/... File src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43760/25/src/mainboard/clevo/kbl-u/... PS25, Line 92: device pci 1c.0 off end # PCI Express Port 1 No luck in getting the Wifi PCIe device to show up by enabling this port either.
``` diff --git a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb index 8a20ca39fc..d6c0f68cd1 100644 --- a/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n240bu/devicetree.cb @@ -89,7 +89,12 @@ chip soc/intel/skylake device pci 19.0 on end # UART 2 device pci 19.1 off end # I2C5 device pci 19.2 off end # I2C4 - device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "2" + register "PcieRpClkSrcNumber[0]" = "2" + register "PcieRpLtrEnable[0]" = "1" device pci 1c.1 on # PCI Express Port 2 chip drivers/wifi/generic device pci 00.0 on end # x1 WLAN ```
``` Allocating resources... Reading resources... PCI: 02:00.0 register 10(ffffffff), read-only ignoring it PCI: 02:00.0 register 14(ffffffff), read-only ignoring it PCI: 02:00.0 register 18(ffffffff), read-only ignoring it PCI: 02:00.0 register 1c(ffffffff), read-only ignoring it PCI: 02:00.0 register 20(ffffffff), read-only ignoring it PCI: 02:00.0 register 24(ffffffff), read-only ignoring it PCI: 02:00.0 register 30(ffffffff), read-only ignoring it Done reading resources. ```