Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40010 )
Change subject: sb/intel/bd82x6x/sata: Fix IDE legacy mode, plus more ......................................................................
Patch Set 3:
(7 comments)
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/sata.c:
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... PS2, Line 131: printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
Into CB:39828, please.
Done
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... PS2, Line 133: /* No AHCI: clear AHCI base */ : pci_write_config32(dev, 0x24, 0x00000000); : : /* And without AHCI BAR no memory decoding */
Felix, this should be a separate change. For the commit message: […]
Done
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... PS2, Line 149: /* Set Interrupt Line */ : /* Interrupt Pin is set by D31IP.PIP */ : pci_write_config8(dev, INTR_LN, 0xff);
Can be a separate change: […]
Done
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... PS2, Line 43: static void sata_read_resources(struct device *dev) : { : struct resource *res; : : pci_dev_read_resources(dev); : : /* Assign fixed resources for IDE legacy mode */ : : u8 sata_mode = 0; : get_option(&sata_mode, "sata_mode"); : if (sata_mode != 2) : return; : : res = find_resource(dev, PCI_BASE_ADDRESS_0); : if (res) { : res->base = 0x1f0; : res->size = 8; : res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; : } : : res = find_resource(dev, PCI_BASE_ADDRESS_1); : if (res) { : res->base = 0x3f4; : res->size = 4; : res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; : } : : res = find_resource(dev, PCI_BASE_ADDRESS_2); : if (res) { : res->base = 0x170; : res->size = 8; : res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; : } : : res = find_resource(dev, PCI_BASE_ADDRESS_3); : if (res) { : res->base = 0x374; : res->size = 4; : res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; : } : } : : static void sata_set_resources(struct device *dev) : { : /* work around bug in pci_dev_set_resources(), it bails out on FIXED */ : u8 sata_mode = 0; : get_option(&sata_mode, "sata_mode"); : if (sata_mode == 2) { : unsigned int i; : for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) { : struct resource *const res find_resource(dev, i); : if (res) : res->flags &= ~IORESOURCE_FIXED; : } : } : : pci_dev_set_resources(dev); : }
Felix, please squash these into CB:39828.
Done
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... PS2, Line 199: printk(BIOS_DEBUG, "SATA: Controller in IDE compat mode.\n");
Into CB:39828, please.
Done
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... PS2, Line 203: printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n");
Into CB:39828, please.
Done
https://review.coreboot.org/c/coreboot/+/40010/2/src/southbridge/intel/bd82x... PS2, Line 260: 1 << 18 | 1 << 14 | 0x04 << 7 | 1 << 3);
Separate change, please. For the commit message: […]
Done