[coreboot-gerrit] Patch merged into coreboot/master: northbridge/intel/gm45: Use TSC for ramstage timer per default

the following patch was just integrated into master:
commit 0819a47d14e8c933dab7089a41625f043778a4c7
Author: Stefan Reinauer 
Date:   Sun Mar 6 01:49:27 2016 -0800

northbridge/intel/gm45: Use TSC for ramstage timer per default

This is a step towards isolating the timer drivers.

Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4
    Signed-off-by: Stefan Reinauer 
    Reviewed-on: https://review.coreboot.org/13922
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth

See https://review.coreboot.org/13922 for details.

-gerrit