Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14819
-gerrit
commit 5b321e95e5c0c6aa97212bca4db62aff09c3adfa Author: Arthur Heymans arthur@aheymans.xyz Date: Thu May 19 16:06:09 2016 +0200
i945: Enable changing VRAM size
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c
The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.
The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states.
What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge.
TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version
Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/mainboard/apple/macbook21/cmos.default | 1 + src/mainboard/apple/macbook21/cmos.layout | 11 ++++++++++- src/mainboard/getac/p470/cmos.layout | 11 ++++++++++- src/mainboard/ibase/mb899/cmos.layout | 12 +++++++++++- src/mainboard/intel/d945gclf/cmos.layout | 11 ++++++++++- src/mainboard/kontron/986lcd-m/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/t60/cmos.default | 1 + src/mainboard/lenovo/t60/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/x60/cmos.default | 1 + src/mainboard/lenovo/x60/cmos.layout | 11 ++++++++++- src/mainboard/roda/rk886ex/cmos.layout | 12 +++++++++++- src/northbridge/intel/i945/early_init.c | 14 +++++++++----- src/northbridge/intel/i945/gma.c | 12 +----------- src/northbridge/intel/i945/i945.h | 2 ++ src/northbridge/intel/i945/northbridge.c | 12 +----------- src/northbridge/intel/i945/ram_calc.c | 13 +++++++++++++ 16 files changed, 113 insertions(+), 35 deletions(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 37018a4..1cf350c 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -17,3 +17,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 4b4b8de..8329347 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -59,7 +59,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -124,6 +126,13 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index 4c40dc7..6d5dc8e 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -59,7 +59,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -112,6 +114,13 @@ enumerations 7 2 Keep 8 0 No 8 1 Yes +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index d1bab31..6aea94f 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -58,7 +58,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -159,6 +161,14 @@ enumerations #10 13 69/156 #10 14 72/161 #10 15 75/167 +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index 0511582..47f48dd 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -58,7 +58,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -106,6 +108,13 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index c614e6f..499bd43 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -58,7 +58,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 12 gfx_uma_size
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -164,6 +166,14 @@ enumerations #10 15 75/167 11 0 No 11 1 Yes +12 0 1M +12 1 4M +12 2 8M +12 3 16M +12 4 32M +12 5 48M +12 6 64M + # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default index 5dd0c70..03b92e3 100644 --- a/src/mainboard/lenovo/t60/cmos.default +++ b/src/mainboard/lenovo/t60/cmos.default @@ -18,3 +18,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 12e7d86..2cd4e7b 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -57,7 +57,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -127,6 +129,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 3579757..4e72734 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -18,3 +18,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 2d9fe41..3e316c9 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -57,7 +57,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -127,6 +129,13 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 4c40dc7..761732e 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -59,7 +59,10 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size +
# coreboot config options: bootloader 416 512 s 0 boot_devices @@ -112,6 +115,13 @@ enumerations 7 2 Keep 8 0 No 8 1 Yes +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M
# ----------------------------------------------------------------- checksums diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ade120f..f4d0916 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,6 +23,7 @@ #include <halt.h> #include <string.h> #include "i945.h" +#include <pc80/mc146818rtc.h>
int i945_silicon_revision(void) { @@ -145,7 +146,7 @@ static void i945_detect_chipset(void)
static void i945_setup_bars(void) { - u8 reg8; + u8 reg8, gfxsize;
/* As of now, we don't have all the A0 workarounds implemented */ if (i945_silicon_revision() == 0) @@ -178,10 +179,13 @@ static void i945_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
- /* Hardware default is 8MB UMA. If someone wants to make this a - * CMOS or compile time option, send a patch. - * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); - */ + /* vram size from cmos option */ + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) + gfxsize = 2; /* 2 for 8MB */ + /* make sure no invalid setting is used */ + if (gfxsize > 6) + gfxsize = 2; + pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
/* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index df13ef4..02caa0a 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -353,17 +353,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); uma_size = 0; if (!(reg16 & 2)) { - reg16 >>= 4; - reg16 &= 7; - switch (reg16) { - case 1: - uma_size = 1024; - break; - case 3: - uma_size = 8192; - break; - } - + uma_size = decode_igd_memory_size((reg16 >> 4) & 7); printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); }
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 0536a36..a7a3c5c 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -364,6 +364,8 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end);
+u32 decode_igd_memory_size(u32 gms); + #endif /* __ACPI__ */
#endif /* NORTHBRIDGE_INTEL_I945_H */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 514f88c..719a795 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -104,18 +104,8 @@ static void pci_domain_set_resources(device_t dev) /* Note: subtract IGD device and TSEG */ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); if (!(reg16 & 2)) { - int uma_size = 0; printk(BIOS_DEBUG, "IGD decoded, subtracting "); - reg16 >>= 4; - reg16 &= 7; - switch (reg16) { - case 1: - uma_size = 1024; - break; - case 3: - uma_size = 8192; - break; - } + int uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); tomk_stolen -= uma_size; diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index b161431..4349d19 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <cbmem.h> #include "i945.h" +#include <console/console.h>
static uintptr_t smm_region_start(void) { @@ -56,3 +57,15 @@ void *cbmem_top(void) { return (void *) smm_region_start(); } + +/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +u32 decode_igd_memory_size(const u32 gms) +{ + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, + 48, 64 }; + + if (gms > ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +}