Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier.
Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81433?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: soc/amd/non_car/memlayout_x86.ld: Top align the code ......................................................................
soc/amd/non_car/memlayout_x86.ld: Top align the code
This does the following: - Top align the bootblock so that the only the memory needed gets used. This might slightly reduce the time the PSP needs to decompress the bootblock in memory - Use a memory directive to assert that the 16bit code is inside the top 64K segment - Use the program counter less. While the BDF linker is happy about running the program counter backwards, LLD is not. There is no downside to this. - Use a symbol rather that the program counter for sections. LLD gets confused when (.) is used along with '<': it places the section at the start of the memory region, rather than at the program counter. Using a variable name works around this. - Use a 'last_byte' section to make sure the first instruction is at 0xfff0. Both the BDF and the LLD linkers seems to work well with this code
TEST: Both BFD and LLD are able to link the bootblock
Change-Id: I18bdf262f9c358aa01795b11efcb863686edc79c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 1 file changed, 22 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/81433/2