[coreboot-gerrit] Change in coreboot[master]: sc7180: Add QUPv3 FW load & config

[Roja Rani Yarubandi (Code Review)]

Roja Rani Yarubandi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35499 )

Change subject: sc7180: Add QUPv3 FW load & config
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Patch Set 44:

(5 comments)

Please review the changes

https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... 
File src/soc/qualcomm/sc7180/qupv3_config.c:

https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... 
PS40, Line 22: 	size_t fw_size;
> You don't need this, so you can just pass NULL to cbfs_boot_map_with_leak().

Done

https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... 
PS40, Line 31: 	switch (protocol) {
> How about just […]

Done

https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... 
PS40, Line 51: 		assert(protocol < SE_PROTOCOL_MAX);
> will do the changes and update patch

Done

https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... 
PS40, Line 53:
> One more thing I just noticed, it would be good to have *some* kind of sanity checking here to make  […]

Done

https://review.coreboot.org/c/coreboot/+/35499/40/src/soc/qualcomm/sc7180/qu... 
PS40, Line 75: 		/* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */
> nit: QcLib really shouldn't reconfigure any UART registers to begin with when being called from core […]

Checking with QcLib team