Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33194 )
Change subject: mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable ......................................................................
mb/google/{hatch, sarien, arcada}: Make HECI1 chip config disable
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD for WHL/CML SoC code to set this HECI1 chip config.
Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 61b712d..112c279 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable heci communication - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" # Enable S0ix diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 767df1f..ce960a7 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,7 +15,7 @@
# FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c96423c..739a849 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -15,7 +15,7 @@
# FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1"