Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37865 )
Change subject: mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0
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Patch Set 4:
Patch Set 4: Code-Review-1
There's no guarantee that SPI0 is the last device to enter S0ix and the first device to wake up from S0ix, hence this could cause races where other IRQs are missed.
As per Kane, this is must for runtime S0ix, can i suggest to do the same in GFX0 _PS0/_PS3 as GFX would be last device to enter into low power mode in runtime S0ix. I have enable ACPI debug to verify the same.
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Gerrit-Project: coreboot
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