[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer: add new generic SPD file

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40108 )

Change subject: mb/google/volteer: add new generic SPD file
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Patch Set 3:
> Patch Set 3:
> > Patch Set 3: Code-Review-2
> >
> > This is not correct. We should be using https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google/volt.... Please see my comment: https://b.corp.google.com/issues/152827558#comment10
>
> Thanks, Furquan.  That comment says that data in the SPD is incorrect. 
> "As per FSP code, this should be 0x21 (i.e. 16 rows, 10 columns). Currently checked in coreboot file is wrong."
>
> But it also says that the currently checked in SPD file is the incorrect one, which would mean that this is the correct one, no?  If so, I will try out this SPD and then fix the currently checked in one accordingly and abandon this CL.

Yes, there are some bytes as mentioned on the bug that you should raise a bug against Intel to check the reason behind using those values.