[coreboot-gerrit] Change in coreboot[master]: xeon_sp/cpx: Enable HWP Intel Speed Shift

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44171 )

Change subject: xeon_sp/cpx: Enable HWP Intel Speed Shift
......................................................................

xeon_sp/cpx: Enable HWP Intel Speed Shift

Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR

Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040

Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa
Signed-off-by: Johnny Lin 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/cpu.c
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 1df5c13..cf903b8 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -64,6 +64,18 @@
    	__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
    setup_lapic();

+	/*
+	 * Set HWP base feature, EPP reg enumeration, lock thermal and msr
+	 * This is package level MSR. Need to check if it updates correctly on
+	 * multi-socket platform.
+	 */
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */
+		msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR |
+			LOCK_THERM_INT);
+		wrmsr(MSR_MISC_PWR_MGMT, msr);
+	}
+
    /* Enable Fast Strings */
    msr = rdmsr(IA32_MISC_ENABLE);
    msr.lo |= FAST_STRINGS_ENABLE_BIT;