Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32334 )
Change subject: Documentation: Explain DDR3 read training ......................................................................
Patch Set 2:
(7 comments)
https://review.coreboot.org/c/coreboot/+/32334/1//COMMIT_MSG Commit Message:
PS1:
Please use the full text width of 75 characters.
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https://review.coreboot.org/c/coreboot/+/32334/1//COMMIT_MSG@13 PS1, Line 13: explenation
explanation
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https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... File Documentation/getting_started/ram_initialization/ddr3_flyby.md:
https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 6: is
are
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https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 9: as on
compared to the
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https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 9: did : terminat
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https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 12: The disadvantage of "fly-by" is the more complex memory training that needs to : be done to find the DATA lane skew.
This is because the DDR2 tree results in all signals reaching the chips at the same time, whereas DD […]
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https://review.coreboot.org/c/coreboot/+/32334/1/Documentation/getting_start... PS1, Line 15:
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